Article

Wafer Bumping: Is the Industry Ready?

From a technology perspective, inherent benefits also offer advantages that should propel the technology. An under-bump metallization (UBM) interface layer between wafer pads and bumps provides better bonding and a barrier to prevent materials migration. Redistribution technology, which involves a rerouting of the interconnections of peripheral bond pads to a new array for the package I/Os, accommodates wider pitches that enable both UBM and larger bumps. The bumps themselves provide electrical, mechanical and thermal interconnection, supplying direct contact between the package and the device. This direct interconnection reduces signal propagation delay and relieves the constraints of power and ground distribution. Finally, replacing wire bonds with bump interconnects reduces package size and weight.

Bump formation technologies

Two commonly used wafer bumping methods are screen deposition and electroplating. Each has a different approach to depositing solder on the wafer, and both have been proven in production for some years. Applications range from under-the-hood electronics to high-end logic and CPUs employing these bumping methods. Pitch, necessary I/O count, start-up cost and volume are critical criteria that dictate which method works best.

Screen deposition is a lower-cost bumping method, generally for pitches greater than 150 µm, practiced by a number of companies today. The process involves squeezing solder paste through a screen stencil to deposit bumps directly to die pads on the wafer. With modified stencils, yields are in the 99% range on all wafer sizes using both eutectic and lead-free materials. According to Joachim Kloeser, CTO at Ekra GmbH (Bönnigheim, Germany), special modifications to traditional screen printers are required. For example, high-resolution vision systems to recognize small structures, flexibility for teaching fiducials, high alignment accuracy, integrated cleaning, automatic wafer handling and high process repeatability must all be incorporated into a successful wafer bumping screen printer machine.

1. Tin/silver bumps created by an electroform process. The highly uniform bump sizes and tight pitches enable cost-effective high-volume bumping processes. (Source: Semitool)

Electroplating technology involves starting at the UBM and performing template, plate, strip, reflow and etch series of processes to form the bump interconnections. Electroplating offers excellent control on deposition rates and uniformity of bumps for void-free formation; variations in bump size can be controlled to within ±1 µm. The bath chemistry and composition must be controlled since it affects properties such as alloy composition, surface roughness or hardness, and crystalline structure. This bumping method can produce much finer bumps in the <100 µm range, with tighter pitches and linewidths and corresponding greater bump densities (Fig. 1). Another benefit of electroplating is that yields significantly outperform screen deposition bumping. While startup costs may be higher, some packaging foundries are now offering 300 mm electroplated wafer-level packaging at very competitive prices, which will drive the overall cost more in line with traditional packaging operations. Since the International Technology Roadmap for Semiconductors (ITRS) forecasts continued reduction in bump pitches, lead-free and power redistribution, electroplating will surely capture market share associated with higher-volume operations.

Some alternative methods of bump formation build on lithography associated with front-end processes and wire bonding borrowed from back-end interconnection processes. In back-end operations, the resist layers are thick (20-100 µm) with large feature sizes (3-150 µm), which pose special challenges to lithography technology. Yet applications demanding smaller-sized bumps with narrower pitches justify some form of lithography.

Forming wafer bumps via lithography can be accomplished by either a photolithography stepper or with a proximity mask aligner, depending on the performance vs. cost equation parameters particular to individual manufacturers. Key subsystems critical to developing a high-performance wafer bumping stepper system include high-fidelity projection lens/illumination, automated substrate alignment, precision X/Y stage, automated reticle handling and storage, and a state-of-the-art suite of metrology sensors. "There is a trend in the industry toward smaller-area array devices and, therefore, feature sizes in the range of 10-15 µm," said Elvino da Silveira, president of Azores Corp. (Wilmington, Mass.). "Azores' photolithography stepper technology is already positioned for that change, with deposition capabilities well beyond traditional technologies."

Stud and gold ball bumping is performed by machines based on wire-bond technology that bump singulated die or entire wafers for high-performance devices, R&D and prototyping, batch runs, and contract assembly production. Gold bumping provides superior electrical and thermal connectivity, low inductance values, reduced electrical loss, clean processing, and lower power requirements. One advantage is that these solderless bump connections eliminate the need for UBM and fluxing.

2. Patented one-step bumps exemplify the use of a thermosonic process using gold wire vs. metal alloys in bumping materials. The sheared tops aid in interconnection to substrates. (Source: Palomer)

Bumps are formed by a modified bonder that uses thermosonic energy to first attach standard 1 mm gold wire to the die pads and then shear the top of the wire without leaving a tail. With the most advanced bonders available today, the result is a planar, flat-top bump that requires no coining in a single-step process (Fig. 2 ). "Gold bumps that are bonded and planarized to a programmable height between 10 and 30 µm with 2 µm co-planarity find application in image sensors, high-brightness LEDs and SAW filters," said Bruce Hueners of Palomar Technologies (Vista, Calif.).

Solder reflow

Solder bumps must undergo a reflow process to become fully stabilized. Since their composition may be high lead content, eutectic or lead-free, the equipment and process must be capable of handling a wide range of temperature profile variations yet maintain tight thermal uniformity within each process profile. The primary danger during reflow is the formation of oxides that degrade subsequent processes. "Two different reflow processes — nitrogen with flux or hydrogen flux-free — can be used to control oxide formation," said Kristen Mattson, semiconductor products manager at BTU International (North Billerica, Mass.). "The flux-based process presents the challenge of integrating the flux coating process and dealing with volatilized flux in the reflow process chamber, while the hydrogen process requires tight atmosphere control." With either process, atmosphere purity and thermal uniformity ensure robust reflow. Two additional measures, a uniform flux coating across the entire wafer and maintaining at least 95% hydrogen purity, will aid in preventing oxide formation. Cleanliness from particulate formation and flux contamination to the equipment and the process are also of paramount importance.

Inspection

Improper wetting with the UBM and excessive flux residue are two common problems that create air gaps resulting in voids. Since bumps typically measure 100-200 µm in diameter, and a voided area of 5-10% of total bump volume will cause collapse, minute amounts of air can create voids. The formation of voids within bumps is a latent defect that jeopardizes the electrical performance of final packaged die in the form of opens, shorts or entire package failure.

Bumping operations employ a suite of quality assurance tools such as optical microscopes, laser, UV, scanners, shear testers and automated optical imaging technologies to measure volume parameters such as bump height, diameter, shape, shear strength and adhesion. Yet high-resolution X-ray is necessary to explore solder mass, and thus potential voids under the bump surface (Fig. 3 ). "Our customers are under increasing pressure to reduce voids in wafer bumps and to improve their overall productivity," said Lance Scott, president and CEO of FeinFocus USA (Stamford, Conn.).

Although much of wafer bumping technology is based on front-end semiconductor techniques, early indications show that wafer bumping has become associated with back-end semiconductor operations. Two industry consortia, Semiconductor Equipment Consortium for Advanced Packaging (SECAP) and the Advanced Packaging and Interconnect Alliance (APiA), have been formed from both front- and back-end equipment providers to enable wafer bumping technologies. Regardless of location performed, the transition to 300 mm wafers is an important catalyst for wafer bumping and the growth of wafer-level packages, because the additional economy of scale for 300 mm wafers makes wafer-level packaging a preferred solution to wire bonding.

However, yield must exceed that of conventional packaging and be racheted up to approximate front-end numbers. And, since packaging itself contributes mightily to total cost, that remains a predominant issue, especially since processing takes place with patterned wafers. One comfort is that, when the technology qualifies on 300 mm tools, smaller wafer sizes are inherently qualified also. However, as with all new technologies, a critical mass must be reached with installed infrastructure and volume growth to derive true cost benefits. Ultimately, wafer bumping technology is real, and applications abound for those pioneers who are ready to exploit its potential.